What is the normal baud rate used

20. USART

20.1 features

  • Two-way communication, i.e. independent sending and receiving
  • Asynchronous and synchronous operation
  • Synchronous operation as master or slave
  • High resolution baud rate generator
  • Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
  • Generation of even and odd parity bits and parity checking by the hardware
  • Data overflow detection
  • Frame error detection
  • Interference filter with detection of incorrect start bits and digital low-pass filter
  • Three separate interrupts when sending finished, sending register empty and receiving data available
  • Multiprocessor communication mode
  • Double speed asynchronous mode

20.2 Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a highly flexible serial component.

The USART0 can also be used as an SPI master, see separate chapter. The PRUSART0 bit in the PRR power reduction register must be cleared in order to use the USART.

Figure 20-1 shows the simplified block diagram of the USART. I / O registers and I / O pins that the CPU can access are shown in bold.

The dashed boxes in the block diagram show the three separate main components of the USART: clock generator, transmitter unit and receiver unit. The control registers are used by all three parts. The logic of the clock generator consists of a synchronization logic for the external clock input, which is used in the synchronous slave mode, and the baud rate generator. The XCK pin (transfer clock) is only used in synchronous transfer mode. The transmitter consists of a simple write buffer, the serial shift register, the parity generator and control logic for handling the various frame formats. The write buffer allows continuous data transfer without delay between the data frames. The receiver is the most complex part of the USART with its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver consists of a parity checker, the control logic, a shift register and a double receive buffer (UDR). The receiver supports the same frame formats as the sender and can detect frame errors, data overflows and parity errors.

Fig. 20-1: USART block diagram
Note:
  1. See Figure 1-1 and Table 14-9 for the location of the connections

20.3 Clock Generation

The clock generation logic generates the basic clock for the transmitter and receiver. The USART supports four clock modes: normal asynchronous mode, double-speed asynchronous mode, synchronous master mode, and synchronous slave mode. The UMSELnBit in USART control register C (UCSRC) selects between asynchronous and synchronous mode. Double the speed (only asynchronous) can be achieved with the U2X bit in the UCSRnA register can be selected. If a synchronous mode (UMSEL = 1) is used, the data direction register for the XCK pin (DDR_XCK) controls whether the clock source is internal (master mode) or external (slave mode). The XCK pin is only active in the synchronous modes. The following figure shows the block diagram of the clock generation logic.

Fig. 20-2: Block diagram of clock generation

Description of the signals:

txclkSend clock (internal signal)
rxclkReceiver base clock (internal signal)
xckiInput from the XCK pin (internal signal), used in synchronous slave mode
xckoClock output to the XCK pin (internal signal), used in synchronous master mode
foscSystem clock frequency, typically crystal frequency

20.3.1 Internal clock

The internal clock generation is used for the asynchronous and the synchronous master mode. The description refers to the picture before.

The USART baud rate register (UBRR) and the down counter work together as a programmable prescaler or as a baud rate generator. The down counter, which is clocked with the system clock (fosc), is loaded with the value from the UBRR every time the counter has reached zero or the UBRR is written. A clock is generated every time the counter reaches zero. This clock is the baud rate generator output clock (= fosc / (UBRR + 1)). The transmitter divides the baud rate generator output clock by 2, 8 or 16, depending on the mode. The baud rate generator output is used directly by the receiver clock and the data recovery units. The recovery units use clock generation that uses 2, 8, or 16 states, regardless of the mode set by the UMSEL, U2X and DDR_XCK bits.

Table 20-1: Determine baud rates
Operating modeequation
Baud rate from UBRRn
equation
UBRRn from baud rate
Asynchronous, normal
U2Xn = 0
BAUD = fOSC
16 (UBRRn – 1)
Asynchronous, twice as fast
U2Xn = 1
Synchronous, master
Note:
  1. The baud rate is the symbol rate in baud

Some examples of UBRR values ​​and frequencies of the system clock are shown in the tables below.

20.3.2 Double the speed

The data transfer rate can be doubled if the U2X bit is set in the UCSRA. Setting this bit only has an effect in asynchronous mode. If a synchronous mode is used, the bit should be left clear.

Setting the bit reduces the divisor of the baud rate divider from 16 to 8, which corresponds to doubling the transfer rate for asynchronous communication. Note that in this case, the receiver will only use half the number of samples (8 instead of 16) in data acquisition and clock recovery and therefore more accurate baud rate settings and system clocks will be required when using this mode. There are no impairments for the transmitter.

20.3.3 External clock

The external clock is used in the synchronous slave mode. The description refers to the previous image.

The external clock from the XCK pin is sampled by a synchronization register. The output of the synchronization register must pass through an edge detector before it can be used for the transmitter and receiver. This process introduces a delay of two CPU clocks, so the maximum external clock frequency of XCK is limited to: Note that fosc depends on the stability of the source of the system clock. It is therefore recommended to allow for some leeway in order to avoid possible data loss due to changes in frequency.

20.3.4 Synchronous clocking

If a synchronous mode has been selected (USEL = 1), then the XCK pin is used either as a clock input (slave) or as a clock output. The relationship between the clock edges, the data sampling or data changes is the same. The basic principle is that the data input (RxD) is scanned with the opposite edge of the XCK cycle than with the edge to which the data output (TxD) changes.

Picture 20-3: Synchronous clock timing diagram

The UCPOL bit in the UCRSC register defines which XCK clock edge is used for sampling the data and which is used for the data exchange. As can be seen in the figure above, if UCPOL = 0, the data is changed with the rising edge of XCK and scanned with the falling edge. With UCPOL = 1, the data is changed with the falling edge and scanned with the rising edge.

20.4. Frame formats

A serial frame is defined as a character containing data with synchronization bits (start and stop bits) and an optional parity bit for error detection. USART accepts all 30 combinations of the following as valid frame formats:

  • 1 start bit
  • 5, 6, 7, 8 or 9 data bits
  • no, even or odd parity bit
  • 1 or 2 stop bits

A frame begins with the start bit, followed by the LSB data bit. The others then follow, up to a total of nine data bits, ending with the MSB. If enabled, a parity bit is inserted after the data bits before the stop bits follow. When a complete frame has been transmitted, another frame can follow directly or the communication connection can be set to an idle (high) state. The following figure shows the possible frame formats, the bits in brackets are optional.

Picture 20-4: Frame formats
St.Start bit (always low)
(n)Data bits (0 to 8)
P.Parity bit, even or odd
SpStop bit (always high)
IDLENo transmission on the communication line (RxD or TxD). An IDLE line must always be high.

The frame format that the USART uses is set by the bits UCSZ2 to UCSZ0, UPM1 to UPM0 and the USBS bit in the registers UCSRB and UCSRC. The receiver and the transmitter use the same settings. It should be noted that changing these bits renders all current transmissions of the sender and receiver unusable.

The bits UCSZ2 to UCSZ0 define the number of data bits in the frame. Bits UPM1 to UPM0 enable the parity bit and its type. The selection between one or two stop bits is made with the USBS bit. The receiver ignores a second stop bit. A frame error is therefore only recognized in those cases in which the first stop bit is zero.

20.4.1 Parity Bit Calculation

The parity is the exclusive OR combination of all data bits. In the case of odd parity, the inversion is used. The relationship between data bits and parity is as follows:
P.just=dn-1 ⊕… ⊕ d3 ⊕ d2 ⊕ d1 ⊕ d0 ⊕ 0
P.odd=dn-1 ⊕… ⊕ d3 ⊕ d2 ⊕ d1 ⊕ d0 ⊕ 1
PevenParity bit using even parity
PoddParity bit using odd parity
dnData bit n of the character

If used, the parity bit is always between the last data bit (MSB) and the first stop bit.

20.5 Initialization

The USART must be initialized before any data transfer can take place. The initialization sequence usually consists of setting the baud rate generator, setting the frame format and enabling the transmitter and receiver depending on which is required. In the case of interrupt-driven USART operation, the global interrupt flag must be cleared during the initialization of the USART (and thus all interrupts disabled).

Before a new initialization with changing the baud rate or the frame format is carried out, one must make sure that no transmission is running while the registers are being changed. The TXC flag can be used to check whether the transmitter has completed all transmissions and the RXD flag can be used to check whether there is no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (i.e. before the UDR is written) if it is to be used in this sense.

The following simple example for the initialization of the USART is identical in assembler and C. The examples assume that polling and not interrupts are used and that a fixed frame format is used. The baud rate is transferred as a parameter of the function. The assembler code assumes that the baud rate parameter is stored in registers R25: R24. If the function writes to the UCSRC register, the URSEL bit (MSB) must be set because UBRRH and UCSRC share an I / O memory cell.

Code example in assembler(1)
USART_Init:; Set baud rate sts UBRR0H, r25 sts UBRR0L, r24; Enable transmitter and receiver ldi r24,1 << RXEN0 | 1 << TXEN0 sts UCSR0B, r24; Set frame format: 8 data bits, 2 stop bits, no parity ldi r24,1 << USBS0 | 3 << UCSZ00 sts UCSR0C, r24 ret
Code example in C(1)
#define F_CPU 1843200 // Clock frequency, can also come from the Makefile #define BAUD 9600 void main (void) {... / * This expression rounds off correctly and generates a constant * / USART_Init ((unsigned) (F_CPU / 16.0 / BAUD- 0.5)); ...} void USART_Init (unsigned ubrr) {/ * set baud rate * / UBRR0 = ubrr; / * Enable transmitter and receiver * / UCSR0B = (1 << RXEN0) | (1 << TXEN0); / * Set frame format: 8 data bits, 2 stop bits, no parity * / UCSR0C = (1 << USBS0) | (3 << UCSZ00); }
Note:
  1. See "About Code Examples"

More advanced initialization routines can be designed in such a way that the frame format is also transferred as a parameter and the interrupts are automatically blocked and enabled, etc. the program can be adopted.

20.6 Send data

The USART sender is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB register. When the transmitter is enabled, the normal port function of the TxD pin is overwritten by the USART and functions as the output of the serial transmitter. The baud rate, the operating mode and the frame format must first be set before a transmission can take place. If the synchronous mode of operation is used, the clock at the XCK pin is used as the send clock.

20.6.1 5-8 data bits

A transfer is started by loading the send buffer with the data to be sent. The CPU loads the send buffer by writing to UDR. The buffered data in the send buffer is transported into the shift register when the shift register is ready to send a new frame. The shift register is loaded when it is idle (i.e. no transmission in progress) or immediately after the last stop bit has been transmitted from the previous frame. When the shift register is loaded with new data, a complete frame is transmitted at a rate that is specified by the baud rate register, the U2X bit or the XCK clock, depending on the operating mode.

The following program example shows a simple USART send function based on polling the flag "data register empty" UDRE. If frames with fewer than 8 data bits are used, the MSBs that were written into the UDR are ignored. The USART must be initialized before the function can be used. The assembler code assumes that the data to be sent are in register R24.

The function waits until the send buffer is empty by querying the UDRE flag before it is loaded with the new data to be sent. If the corresponding interrupt is used, the interrupt routine writes the data to the send buffer.

20.6.2 9 data bits

If 9-bit characters are used (UCSZ = 7), the ninth bit is written to the TXB8 bit in the UCSRB register before the low byte of the character is written to UDR. The following sample program shows the function for sending a 9-bit character. In the assembler example it is assumed that the data to be sent are in registers R25 and R24.

Hints:
  1. The send function is general. It can be optimized so that the content of the UCSR0B register is static. For example, the TXB8 bit could be loaded once in the initialization.
  2. See "About Code Examples"

The ninth bit can be used to identify an address frame in multiprocessor communication or for other protocol tasks such as synchronization.

20.6.3 Send flags and interrupts

The USART sender has two flags that identify the following statuses: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used to generate an interrupt.

The Data Register Empty Flag (UDRE) signals that the send buffer is ready to accept new data. This bit is set when the send buffer is empty and is cleared when the send buffer contains data to be sent that has not yet been transferred to the shift register. To ensure compatibility with future blocks, the bit should always be set to zero when writing to the UCSRA register.

If the Data Register Empty Interrupt Enable (UDRIE) bit in the UCSRB register is set to 1, the corresponding interrupt will be executed as long as the UDRE flag is set, provided that the interrupts are globally enabled. The UDRE Falg is deleted by writing to the UDR. If an interrupt-controlled data transfer is used, the interrupt routine must either write a new date in the UDR in order to clear the UDRE flag or block the data register Empty Interrupt, otherwise a new interrupt will be triggered as soon as the interrupt routine has ended.

The Transmit Complete (TXC) flag is set when a complete frame has been transmitted from the sender's shift register and there is no further data in the transmit buffer. The TXC flag is automatically cleared when the transmit complete interrupt is executed or by writing a 1 in the bit. The TXC bit is useful for half-duplex interfaces (such as the RS485 standard), where the sending unit has to go into receive mode in order to enable the communication bus after a successful transmission.

If the Transmit Complete Interrupt Enable (TXCIE) bit is set in the UCSRB, the USART Transmit Complete Interrupt is executed as soon as the TXC flag is set, provided that the interrupts are globally enabled.If the interrupt is used, the interrupt routine of the TXC Falg does not have to be cleared, as this happens automatically when the interrupt routine is executed.

20.6.4 Parity generator

The parity generator calculates the parity bit for the serial frame data. If the parity bit is enabled (UPM1 = 1), the sender control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is being sent.

20.6.5 Deactivating the transmitter

Blocking the transmitter by setting the TXEN to zero does not take effect until an ongoing or pending transmission has been completed. This means that the lock only takes effect when the sender's shift register and the send buffer no longer contain any data to be sent. When the transmitter is locked, it will no longer overlay the TxD pin.

20.7 Receive data

The USART receiver is enabled by setting the Receive Enable (RXEN) bit in the UCSRB register to 1. When the receiver is enabled, the normal function of the RxD pin is overwritten by the function of the USART receiver input. The baud rate, the operating mode and the frame format must be set before the first serial reception can take place. When synchronous mode is used, the clock from the XCK pin is used as the transfer clock.

20.7.1 5-8 data bits

The receiver starts receiving data when it detects a valid start bit. Each bit that follows is scanned with the baud rate or the XCK clock and shifted into the receive shift register until the first stop bit of the frame is received. The second stop bit is ignored by the receiver. When the first stop bit has been received, i.e. a complete serial frame is in the input buffer, the content of the shift register is shifted into the receive buffer. The receive buffer can then be read out by reading the UDR I / O memory cell.

The following sample program shows a simple USART receive function based on polling the Receive Complete (RXC) flag. If frames with fewer than 8 data bits are used, the MSB that are read from the UDR are masked with zero. The USART must be initialized before the function can be used. The function waits until there is data in the receive buffer by permanently polling the RXC flag before reading out the buffer.

20.7.2 9 data bits

If 9-bit characters are used (UCSZ = 7), the ninth bit must be read from the RXB8 bit in the UCSRB register before the low byte is read from the UDR. This rule also applies to the FE, DOR and PE status flags. First read the status of UCSRA, then the data from the UDR. Reading the UDR I / O memory cell changes the status of the receive buffer FIFO and thus the TXB8, FE, DOR and PE bits that are stored in the FIFO are also changed.

The following sample program shows a simple USART receive function that handles the status bits and the 9-bit character.
Code example in assembler(1)
USART_Receive:; Wait for data to be received lds r16, UCSR0A sbrs r16, RXC0 rjmp USART_Receive; Get status and 9th bit, then data from buffer lds r18, UCSR0A lds r17, UCSR0B lds r16, UDR0; If error, return -1 andi r18, (1 << FE0) | (1 << DOR0) | (1 << UPE0) breq USART_ReceiveNoError ldi r17, HIGH (-1) ldi r16, LOW (-1) USART_ReceiveNoError:; Filter the 9th bit, then return lsr r17 andi r17,0x01 ret
Code example in C(1)
unsigned int USART_Receive (void) {unsigned char status, resh, resl; / * Wait for data to be received * / while (! (UCSR0A & (1 << RXC0))); / * Get status and 9th bit, then data from buffer * / status = UCSR0A; resh = UCSR0B; resl = UDR0; / * If error, return -1 * / if (status & (1 << FEn) | (1 << DORn) | (1 << UPEn)) return -1; / * Filter the 9th bit, then return * / resh = (resh >> 1) & 0x01; return ((resh << 8) | resl); }
Note:
  1. See "About Code Examples"
    For I / O Registers located in extended I / O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I / O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The receive function reads all I / O registers into the file register before another calculation is carried out. This enables optimal utilization of the receive buffer, since the receive buffer is emptied by reading it out and is therefore ready as early as possible to accept new data.

20.7.3 Receive complete flag and interrupt

The USART has a flag that signals its status. The Receive Complete Flag (RXC) indicates that unread data is in the receive buffer. The bit is 1 if there are unread data in the receive buffer and it is 0 if the receive buffer is empty, i.e. if it does not contain any unread data. If the receiver is blocked (RXEN = 0), the receive buffer is emptied and consequently the RXC bit is deleted.

If the Receive Complete Interrupt Enable (RXCIE) bit is set in the UCSRB register, the USART Receive Complete Interrupt is executed as long as the RXC flag is set, provided that the interrupts are globally enabled. If an interrupt-controlled data reception is used, the interrupt routine must read out the received data from the UDR register in order to clear the RXC flag. Otherwise, a new interrupt occurs immediately after the interrupt routine has ended.

20.7.4 Receive error flags

The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All flags can be accessed by reading the UCSRA register. The error flags are stored in the input buffer together with the frame for which they signal the error status. Since the error flags are also buffered, the UCSRA register must be read out before the receive buffer (UDR) is read, since reading the UDR I / O memory cell changes the buffer reading point. Another property of the error flags is that they cannot be changed by being written by the software. Nevertheless, all flags must be set to zero when writing to the UCSRA register in order to ensure compatibility with future USART expansions. None of the error flags trigger an interrupt.

The Frame Error (FE) flag shows the status of the first stop bit of the next frame to be read, which is in the receive buffer. The FE bit is zero if the stop bit was read correctly (as 1) and the bit is one if the stop bit was incorrect (i.e. 0). This bit can therefore be used to detect synchronization errors, aborts or protocol errors. The FE flag is not influenced by setting the USBS bit in the UCSRC register, as the receiver ignores all stop bits except the first. To ensure compatibility with future blocks, the bit should be set to 0 when writing to the UCSRA register.

The Data OverRun Flag (DOR) signals a loss of data due to the overflow of the receive buffer. A data overflow occurs when the receive buffer is full (i.e. contains two characters), a new character is waiting in the receive shift register and a new start bit is recognized. If the DOR flag is set, one or more frames between the last frame read and the next frame that can be read from the UDR have been lost. To ensure compatibility with future blocks, the bit should be set to 0 when writing to the UCSRA register. The DOR flag is cleared when a received frame has been successfully transported from the shift register to the input buffer.

The parity error flag (PE) indicates that the next frame in the receive buffer had a parity error when it was received. If the parity check is not enabled, the PE bit is always read as 0. To ensure compatibility with future blocks, the bit should be set to 0 when writing to the UCSRA register.

20.7.5 Parity checker

The parity checker is active when the upper USART parity mode bit (UPM1) is set. The type of parity check (even or odd) is determined by the UPM0 bit. If enabled, the parity checker calculates the parity of the data bits of the incoming frame and compares the result with the parity bit of the frame. The result of the comparison is saved in the receive buffer together with the received data and stop bits. The parity error flag (PE) can then be read out by the software to check whether the frame has a parity error.

The PE bit is set if the next character that can be read from the receive buffer had a parity error when it was received and the parity check was enabled at that moment (UPM1 = 1). The bit is valid until the receive buffer is read.

20.7.6 Deactivation of the recipient

In contrast to the sender, locking the receiver takes effect immediately. The data of an ongoing reception are therefore lost. If the receiver is blocked (RXEN is set to 0), the receiver no longer overwrites the normal function of the RxD port pin. The receiver buffer FIFO is flushed when the receiver is blocked. The remaining data in the buffer is deleted.

20.7.7 Clear the receive buffer

The receiver buffer FIFO is emptied when the receiver is blocked, i.e. the buffer is emptied of its contents. This means that unread data is lost. If the buffer is to be emptied during normal operation, for example due to an error, the UDR I / O register should be read until the RXD flag becomes zero. The following example shows how the input buffer can be emptied.
Note:
  1. See "About Code Examples"
    For I / O Registers located in extended I / O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I / O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

20.8 Asynchronous data reception

The USART contains a clock and data recovery unit to handle asynchronous data reception. The clock recovery logic is used to synchronize the internal clock of the baud rate generator with the incoming serial frame on the RxD pin. The data recovery logic samples every incoming bit and filters it in a low pass. This improves the receiver's susceptibility to failure. The working range for asynchronous reception depends on the accuracy of the internal baud rate clock, the accuracy of the incoming frame and the number of bits per frame.

20.8.1 Asynchronous clock regeneration

The clock recovery logic synchronizes the internal clock with the incoming serial frame. The following figure shows the scanning process of the start bit of an incoming frame. The sampling rate is 16 times the baud rate in normal mode and 8 times the baud rate in double speed mode. The arrows show the synchronization deviations in the scanning process. Note the greater time deviation when using the double speed mode (U2X = 1). The samples labeled zero are samples taken when the RxD line was inactive.
Picture 20-5: Start bit acquisition
When the clock recovery logic detects a high (inactive) to low (start bit) transition on the RxD line, the start bit detection sequence begins. Assume that sample 1 was the first zero sample. Then, in normal mode, the clock recovery logic uses the 8, 9 and 10 samples to determine if a valid start bit was received. In the double speed mode, samples 4, 5 and 6 are used. If two or more of the three samples are detected as high, the start bit is interpreted as a glitch and the receiver waits for the detection of the next high-low transition. Whenever a valid start bit is detected, the clock recovery logic is synchronized and data recovery can begin. The synchronization process is repeated with each start bit.

20.8.2 Asynchronous data regeneration

When the receiver clock is synchronized by the start bit, data recovery can begin. The data recovery unit also scans 16 times in normal mode and 8 times in double-speed mode. The following figure shows the scanning of a data bit or the parity bit. Each scan is given a number that corresponds to the status of the recovery unit.
Picture 20-6: Data and parity bit capture
The decision about the logic level of the received bit is made by the three samples in the middle (number in a box) of the sample sequence by majority decision. The majority decision runs as follows: If two or all samples have a high level, the received bit is recognized as 1, if two or all samples have a low level, the received bit is recognized as 0. The majority decision process works like a low pass filter for the signals arriving via the RxD pin. The recovery process is repeated until a complete frame has been received, including the first stop bit. Please note: The receiver only evaluates the first stop bit.

The following figure shows the sampling of the stop bit and the earliest possible start of the start bit of the next frame.
Picture 20-7: Stop bit and next start bit detection
The majority decision is the same for the stop bit as for the other bits of a frame. If the stop bit is recognized as 0, the Frame Error (FE) flag is set.

A new high-low transition, which indicates the start bit of a new frame, can come immediately after the last bit that is required for the majority decision. In normal mode, the first low level can be sampled at point (A). In double speed mode, the first low level must wait until point (B). The point (C) indicates a full length stop bit. The early start bit detection has an influence on the working range of the recipient.

20.8.3 Asynchronous work area

The working range of the receiver depends on the mismatch between the received bit rate and the internal baud rate. If the sender sends the frames with too high or too low a bit rate or the internal baud rate of the receiver does not have the same base frequency, it is not possible for the receiver to synchronize the frames with the start bit. The following equations can be used to calculate the ratio of the incoming data rate to the internal baud rate.
R.slowly =(D. + 1)·S.
S. - 1 + D · S + S.F.
R.fast =(D. + 2)·S.
(D. + 1)·S. + S.M.
D.Sum of the character size and the size of the parity bit
S.Samples per bit (S = 16 in normal mode, S = 8 in double speed mode)
SFFirst sample number for majority decision (SF = 8 in normal mode, SF = 4 in double speed mode)
SMMiddle sample number for majority decision (SM = 9 in normal mode, SM = 5 in double speed mode)
R.slowlyis the ratio of the lowest incoming data rate that can be accepted to the baud rate of the receiver
R.fastis the ratio of the highest incoming data rate that can be accepted to the baud rate of the receiver

The following tables show the maximum baud rate error of the receiver that can be tolerated. Please note that larger deviations in the baud rate are tolerated in normal mode.

Table 20-2: Recommended maximum receiver baud rate error for normal speed
Data-
+ Parity bits
R.slowly
in %
R.fast
in %
Max. Total error
in %
Recommended max.
Mistake in %
593,20106,67+6,67/-6,8± 3,0
694,12105,79+5,79/-5,88± 2,5
794,81105,11+5,11/-5,19± 2,0
895,36104,58+4,58/-4,54± 2,0
995,81104,14+4,14/-4,19± 1,5
1096,17103,78+3,78/-3,83± 1,5
Table 20-3: Recommended maximum receiver baud rate error for double speed
Data-
+ Parity bits
R.slowly
in %
R.fast
in %
Max. Total error
in %
Recommended max.
Mistake in %
594,12105,66+5,66/-5,88± 2,5
694,92104,92+4,92/-5,08± 2,0
795,52104,35+4,35/-4,48± 1,5
896,00103,90+3,90/-4,00± 1,5
996,39103,53+3,53/-3,61± 1,5
1096,70103,23+3,23/-3,30± 1,0
The recommendations for the maximum baud rate error of the receiver were calculated on the assumption that the sender and receiver share the maximum error equally.

There are two important sources of the receiver's baud rate error. The system clock (XTAL) of the receiver always has low instabilities in the voltage and temperature range. If a crystal is used to generate the system clock, this is rarely a problem. But with a resonator the system clock can deviate by 2%, which depends on the tolerance of the resonator. The second source of error is easier to control. The baud rate generator cannot always divide the system clock down exactly to the desired baud rate. In this case, a UBRR value can be used that brings an acceptably small deviation.

20.9 Multiprocessor communication

Setting the multi-processor communication mode (MPCM) bit in the UCSRA register activates a filter function for the frames received from the USART. Frames that do not contain any address information are ignored and not transferred to the receive buffer.This reduces the number of incoming frames that have to be handled by the CPU in a system with communication between several MCUs via the same data bus. The transmitter is not influenced by the settings of the MPCM bit, but it must be used differently if it is part of a multi-processor communication system.

If the receiver is set to receive frames with 5 to 8 data bits, the first stop bit indicates whether the frame contains data or address information. If the receiver is set from frames with 9 data bits, the ninth bit (RXB8) is used to distinguish address and data information. If the frame type bit (first stop bit or ninth bit) is at 1, the frame contains an address, if the frame type is 0, the frame contains data.

The multiprocessor communication mode enables multiple slave MCUs to receive data from the master MCU. This is possible because the address frame is first decoded to determine which MCU has been addressed. If a certain slave MCU has been addressed, the following data frames will be received normally, while the other slave MCUs ignore them until another address frame is received.

20.9.1 Use of multiprocessor communication

An MCU that works as a master MCU can use the 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or deleted when a data frame (TXB8 = 0) is sent. In this case, the slave MCUs must also be set to the 9-bit character frame format.

The following procedure should be used when exchanging data in multiprocessor mode:
  1. Set all slaves to multiprocessor mode (MPCM in UCSRA to 1)

  2. The master MCU sends an address frame that all slaves receive and read. In the slave MCU, the RXD flag is set in the OCSRC register as usual.

  3. Each slave reads the UDR register and determines whether it has been addressed. If so, it clears the MPCM bit in the PCSRA register, if not, it waits for the next address byte and keeps the MPCM settings.

  4. The addressed MCU receives all data farms until a new address frame is received. The other slave MCUs, for which the MPCM bit is still set, ignore the data farms.

  5. When the last data frame has been received by the addressed MCU, the addressed MCU also sets the MPCM bit to 1 again and waits for the next address frame from the master. The process is then repeated from step 2.
The use of 5 to 8-bit character frame formats is possible, but impractical, since the recipient has to switch between the use of n and n + 1 character frame formats. This makes full-duplex operations difficult, since the sender and the receiver must have the same character width settings. If 5 to 8-bit character frame formats are used, the transmitter must be set to two stop bits (USBS = 1), since the first stop bit is used to identify the frame type.

You should not use read-modify-write commands (SBI and CBI) to set and clear the MPCM bit. The MPCM bit is located in the same I / O memory cell as the TXC flag and this can be accidentally cleared when an SBI or CBI command is executed.

20.10 Examples for the baud rate setting

For standard crystal and resonator frequencies, the most frequently used baud rates can be generated in asynchronous mode using the settings of the UBRR as shown in the following tables. UBRR values ​​whose percentage deviation from the exact baud rate is less than 0.5% are shown in bold. Higher error rates can be accepted, but the receiver then has a poorer immunity to interference, especially with long serial frames (see asynchronous mode of operation). The error value can be calculated using the following formula:
Error [%] = (baud ratenext value-1)· 100 %
baud rate

20.11 Register description

20.11.1 UDRn - bidirectional data register

bit76543210
(0xC6)RxB [7: 0]UDR0 (read)
(0xC6)TxB [7: 0]UDR0 (write)
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000

The USART transmitter data buffer register and the receiver data buffer register share the same I / O memory location, which is referred to as the USART data register or UDR. The Sender Data Buffer Register (TXB) is the destination for data that is written to the UDR. Reading the UDR register will return the contents of the receiver data buffer register (RXB). With 5, 6 or 7 bit characters, the upper, unused bits are ignored by the sender and set to zero by the receiver.

The send buffer can only be written if the UDRE flag is set in the UCSRC register. Data that is written to the UDR when the UDRE flag is not set is ignored by the sender. If data has been written into the transmitter buffer and the transmitter is enabled, the transmitter will load the data into the shift register as soon as the shift register is empty. Then the data is sent out serially via the TxD pin.

The receiver buffer consists of two FIFOs. The FIFOs change their status when the receiver buffer is accessed. Because of this behavior of the receiver buffer, no read-modify-write commands should be applied to this memory location. One must also be careful when using bit test commands, as these also change the status of the FIFO.

20.11.2 UCSRnA - control and status register A

bit76543210
(0xC0)RXC0TXC0UDRE0FE0DOR0UPE0U2X0MPCM0UCSR0A
accessR.R / WR.R.R.R.R / WR / W
Starting value00100000
  • Bit 7 - RXC: USART Receive Complete
This bit is set when there is unread data in the receiver buffer and the bit is cleared when the receiver buffer is empty, i.e. does not contain any unread data. If the receiver is blocked, the receiver buffer is deleted and the RXC bit is set to zero. The RXC Falg can be used to trigger a Receive Complete Interrupt (see RXCIE bit).
  • Bit 6 - TXC: USART Transmit Complete
This bit is set when a frame in the sender shift register has been pushed out completely and no further data is waiting in the sender buffer (UDR). The TXC flag is automatically cleared when the transmit complete interrupt is executed or a logical 1 is written to this bit. The TXC Falg can be used to trigger a transmit complete interrupt (see TXCIE bit).
  • Bit 5 - UDRE: USART Data Register Empty
The UDER flag indicates that the transmitter buffer is ready to accept new data. If UDRE is 1, the buffer is empty and new data can be written to. The UDRE Falg can be used to trigger a Data Register Empty Interrupt (see UDRIE bit). After a reset, the UDRE bit is set and indicates that the transmitter is ready. This bit is set if the next character in the receiver buffer had a frame error when receiving, i.e. when the first stop bit of the next character in the receiver buffer was zero. This bit is valid until the receive buffer is read. The FE bit is zero if the stop bit of the received data was 1. The bit should always be set to 0 when writing to the UCSRA register.
  • Bit 3 - DOR: Data OverRun
This bit is set when a data overflow condition is detected. A data overflow occurs when the receive buffer is full (contains two characters), another character is waiting in the receive shift register and a new start condition is recognized. This bit is valid until the receive buffer is read. The bit should always be set to 0 when writing to the UCSRA register. This bit is set if the next character in the receive buffer had a parity error when it was received and the parity check was enabled at this point in time (UPM = 1). This bit is valid until the receive buffer is read. The bit should always be set to 0 when writing to the UCSRA register.
  • Bit 1 - U2X: Double the USART transmission speed
This bit only has an effect in asynchronous mode. The bit should be set to zero in synchronous mode. If the bit is written with a 1, the divider of the baud rate generator is set from 16 to 8, which results in a doubling of the transmission rate in asynchronous mode.
  • Bit 0 - MPCM: Multi-processor communication mode
This bit enables the multiprocessor communication. If the MPCM bit is set to 1, all incoming frames that do not have address information are ignored by the USART receiver. The sender is not influenced by the MPCM bit.

20.11.3 UCSRnB - control and status register B

bit76543210
(0xC1)RXCIE0TXCIE0UDRIE0RXEN0TXEN0UCSZ02RXB80TXB80UCSR0B
accessR / WR / WR / WR / WR / WR / WR.R / W
Starting value00000000
  • Bit 7 - RXCIE: USART RX Complete Interrupt Enable
Setting this bit to 1 enables the interrupt for the RXC flag. The USART Receive Complete Interrupt is only executed if RXCIE is set to 1, the interrupts are globally enabled and the RXC flag is set in the UCSRA.
  • Bit 6 - TXCIE: TX Complete Interrupt Enable
Setting this bit to 1 enables the interrupt for the TXC flag. The USART transmit complete interrupt is only executed if TXCIE is set to 1, the interrupts are globally enabled and the TXC flag is set in UCSRA.
  • Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Setting this bit to 1 enables the interrupt for the UDRE flag. A data register Empty Interrupt is only executed if UDRIE is set to 1, the interrupts are globally enabled and the UDRE flag is set in UCSRA.
  • Bit 4 - RXEN: Receiver Enable
Setting this bit to 1 enables the USART receiver. The receiver overwrites the normal port function of the RxD pin when it is enabled. Locking the receiver clears the receiver buffer and makes the FE, DOR and PE flags invalid.
  • Bit 3 - TXEN: Transmitter Enable
Setting this bit enables the USART transmitter. The transmitter overwrites the normal port function of the TxD pin when it is enabled. The blocking of the sender (set TXEN to 0) only takes effect when ongoing and waiting transfers have been completed, i.e. when the sender shift register and the sender buffer no longer contain any data to be transferred. After locking, the TxD port is no longer overwritten.
  • Bit 2 - UCSZ2: Character size 2
Together with the UCSZ1 and UCSZ0 bits in the UCSRC register, this bit defines the number of bits per character in a frame for the receiver and the sender.
  • Bit 1 - RXB8: Receive Data Bit 8
The RXB8 bit is the ninth data bit of the received character when working with frames with nine data bits. It must be read before the lower bits are read from the UDR register.
  • Bit 0 - TXB8: Transmit Data Bit 8
The TXB8 bit is the ninth data bit of the character to be sent when working with frames with nine data bits. It must be written before the lower bits are written into the UDR register.

20.11.4 UCSRnC - control and status register C

bit76543210
(0xC2)UMSEL01UMSEL00UPM01UPM00USBS0UCSZ01UCSZ00UCPOL0UCSR0C
accessR / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000110
This bit selects between access to the UCSRC or the UBRRH register. It is read as 1 when the UCSRC register is read. The URSEL bit must be 1 when writing to the UCSRC register.
  • Bit 6 - UMSEL: USART Mode Select
This bit selects between the asynchronous and the synchronous operating mode. When UMSEL = 0, the asynchronous operating mode is selected; when UMSEL = 1, the synchronous operating mode is selected.
Table 20-8: Values ​​for UMSELn-Bits
SHIFT 1SHIFT0mode
00Anynchronous USART (i.e. ART)
01Synchronous USART (i.e. SRT)
10reserved
11SPI Master (MSPIM)(1)
Note:
  1. See USART in SPI mode for a description of the SPI master operating mode
  • Bit 5 and 4 - UPM1, UPM0: Parity mode
These bits enable the parity check and set its type. If enabled, the sender automatically generates and sends the parity of the data sent in each frame. The receiver generates the parity value for the incoming data and compares this with the settings of the UPM0 bit. If no match is detected, the PE flag is set in the UCSRA register.
Table 20-9: Values ​​for UPMn-Bits
UPMn1UPMn0Parity mode
00No parity bit
01reserved
10Even parity
11Odd parity
  • Bit 3 - USBS: Stop Bit Select
This bit defines the number of stop bits that are inserted by the transmitter. With USBS = 0 a stop bit is inserted, with USBS = 1 two stop bits are inserted. The receiver ignores the settings of the USBS bit.
Table 20-10: Values ​​for the USBS bit
USBSnStop bits
01 bit time
12 bit times
  • Bit 2 and 1 - UCSZ1, UCSZ0: Character size 1 and 0
Together with the UCSZ2 bits in the UCSRB register, these bits define the number of bits per character in a frame for the receiver and the sender.
Table 20-11: Values ​​for UCSZn bits
UCSZn2UCSZn1UCSZn0Character length
0005 bits
0016 bit
0107 bit
0118 bit
100reserved
101reserved
110reserved
1119 bit
  • Bit 0 - UCPOL: clock polarity

This bit is only used in synchronous mode. In asynchronous mode, the bit must be written with a zero. The UCPOL bit defines the relationship between the change of the output data and the sampling of the input data and the synchronous clock signal (XCK).

20.11.5 UBRRn - Baud rate register

bit15141312111098
(0xC5)----UBRR0 [11: 8]UBRR0H
(0xC4)UBRR0 [7: 0]UBRR0L
bit76543210
accessR.R.R.R.R / WR / WR / WR / W
R / WR / WR / WR / WR / WR / WR / WR / W
Starting value00000000
00000000
These bits are reserved for future extensions. To ensure compatibility, these bits must be written with zero when UBRRH is written.
  • Bit 11 to 0 - UBRR11 to UBRR0: USART Baud Rate Register
These bits together form a 12-bit register, which contains the USART baud rate. The UBRRH contains the four uppermost bits and the UBRRL the eight lower bits of the USART baud rate. Current transmissions from the sender and receiver become unusable if the baud rate is changed. Writing in the UBRRL register results in an immediate update of the baud rate prescaler.